Question

Two answers required. In CMOS (“C moss”) logic, the similar circuits implementing these two operations have logical efforts of 4/3 and 5/3. Those circuits implementing these operations consist of two PMOS (“P moss”) transistors in parallel and two NMOS (“N moss”) transistors (-5[1])in series, and (15[1])vice versa. These two operations name contrasting architectures (15[1])where floating-gate memory cells are either connected in series or in parallel to the bit line. Simple set-reset latches consist of cross-coupled logic gates implementing either of these two operations. These two operations, which are dual to each other, (15[1]-5[1])are also called (*) Peirce’s (“purses”) arrow and (10[1])the Sheffer stroke. These operations (-5[1])name the two main types of flash memory. Each of these logic gates can be solely used to reproduce all other gates, (10[1])thus making them the two “universal” gates. For 10 points, name these two Boolean operations, the negations of logical conjunction and disjunction. ■END■ (10[4])

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